1. Field of the Invention
The present invention relates to a semiconductor device structure, and more particularly, to a dummy structure of a semiconductor device, which can increase carrier mobility using a channel strain, and a method of fabricating the semiconductor device structure.
2. Description of the Related Art
As complementary metal oxide semiconductor (CMOS) fabrication processes become finer, methods of increasing carrier mobility are necessary. The best method for increasing carrier mobility is to use a strain layer to apply strain to a channel region. FIG. 1 is a cross-sectional view of a gate structure of a semiconductor device using a channel strain technique. Referring to FIG. 1, silicon germanium (SiGe) layers 3 are formed on both sides of a gate electrode 2. Source/drain regions 4 defined in the silicon substrate 1 are formed under the SiGe layers 3. Because the SiGe layers 3 that are epitaxially grown on the silicon substrate 1 have a larger lattice constant than that of silicon of the silicon substrate 1, the grown SiGe layers 3 tend to extend in a lateral direction. Therefore, a channel region (not shown) formed between the SiGe layers 3 experiences compressive stress as indicated by the arrows in the figure. Silicon of the silicon substrate 1 experiencing the compressive stress due to the strain layers, i.e., the SiGe layers 3, has a higher carrier mobility than conventionally used silicon, thereby improving the performance of the semiconductor device. In particular, the compressive stress due to the SiGe layers 3 is used to increase hole mobility in a p-channel metal-oxide-semiconductor (PMOS) region.
In the conventional CMOS fabrication processes, however, a loading effect occurs when the SiGe layers 3 are epitaxially grown as the strain layers. The loading effect is a phenomenon where the growth rate of SiGe is different depending on an area of an active region where SiGe will be grown. That is, the growth rate of SiGe is high in an isolation region where patterns having a large active region are formed, while the growth rate of SiGe is low in a dense region where patterns having a small active region are formed. Therefore, thicknesses of the SiGe layers 3 are different due to the difference of the growth rate in the isolation region and the dense region.
FIG. 2 is a cross-sectional view illustrating the thickness difference of the SiGe layers 3a and 3b respectively grown in the isolation region and the dense region. Referring to FIG. 2, the thicknesses of the SiGe layers 3b formed in the dense regions between gate electrodes 2 are less than those of the SiGe layers 3a formed widely in the isolation region. If the thicknesses of the SiGe layers 3a and 3b are different from each other, the degree of compressive stress affecting a channel region is different. Therefore, device characteristics are different in each region, thereby resulting in the degradation of reliability of the semiconductor device.
An active dummy and a gate dummy are used for preventing dishing and erosion when a chemical mechanical polishing (CMP) process is performed for planarization during the formation of an active region and planarization of an interlayer insulation layer formed on the gate electrodes 2. FIG. 3A is a plan view illustrating the conventional arrangement of active region dummies 1b and gate dummies 2b. FIG. 3B is a cross-sectional view of the active region dummies 1b and the gate dummies 2b. In FIGS. 3A and 3B, an active region 1a and a gate electrode 2a are shown. Referring to FIGS. 3A and 3B, the gate dummy 2b overlaps with the active dummy 1b. In this case, a portion of the active dummy 1b is covered by the gate dummy 2b, so that a region where epitaxial SiGe layers can be formed thereon is reduced. Therefore, the loading effect still exists during the growth of the epitaxial SiGe layers. However, the dishing and erosion problem occurs during the CMP process when the gate dummy 2b is removed so as to expose the top surface of the active dummy 1b. This problem can also occur even though other materials instead of epitaxially grown SiGe are formed to induce channel strain.